The present invention generally relates to a potential comparing circuit, and more particularly to a potential comparing circuit used for a memory device or an A/D converter.
FIG. 1 is a circuit diagram of a conventional potential comparing circuit. The potential comparing circuit shown in FIG. 1 comprises an input transistor (p-type) 1, an output transistor (p-type) 2, a normal input active transistor 3 (n-type) and an inverse input active transistor 4 (n-type). The input transistor 1 and the output transistor 2 constitute a current-mirror circuit 11.
A power input terminal 5 is provided on the current-mirror circuit side, and another power input terminal 6 is provided on the active transistor side. A normal input terminal 7 is provided to the active transistor 3 and an inverse input terminal 8 is provided to the active transistor 4.
An output terminal 9 is connected to a connection point between a drain of the active transistor 4 and a drain of the output transistor 2 of the current-mirror circuit 11. The output terminal 9 is connected to an input terminal of a next-stage logic circuit 10 which comprises, for example, an inverter.
The current-mirror circuit 11 has a saturation current characteristic proportional to a current flowing in the active transistor 3 of the normal input side, and acts as a load against the active transistor 4 of the inverse input side. Output potential level of the output terminal 9 is determined by the load.
If the normal input and inverse input are at the same potential level, each of the active transistors 3 and 4 shows the same saturation current characteristic, and thus the output transistor 2 of the current-mirror circuit 11 also shows a saturation current characteristic proportional to the saturation current characteristic of the active transistors 3 and 4. In this state, if a conductance of each of the transistors 1, 2, 3 and 4 has been adjusted so that the saturation current of the active side becomes equal to that of the load side, a predetermined fixed potential level determined by an intersection of characteristic curves of the active side and the load side is obtained at the output terminal 9. The predetermined fixed potential level is somewhere between potential levels of power sources of the active side and the current-mirror side.
If the potential level of the inverse input shifts in a direction in which the saturation current of the active transistor 4 increases, the intersection of the characteristic curves shifts toward the potential level of the power source of the active side transistor. On the other hand, in a reverse condition, the intersection shifts toward the potential level of the power source of the current-mirror circuit side. In this way, the input potential levels can be compared with each other.
However, in the above-mentioned conventional potential comparing circuit, a determination error may occur in the comparison result because the potential level (comparison result potential level) at the output terminal 9, which potential level is obtained in a condition in which both input potential levels are the same, does not always equal to specific determination potential levels, corresponding to "0" and "1", of the next-stage logic circuit 10.
It is considered that there are two causes for the above determination error. One cause is that the output potential level of the potential comparing circuit, when both of the input potential levels are the same, varies according to the potential level of both of the input potential levels. This cause is dependent on a characteristic of the MOS diode of the current-mirror circuit 11.
The other cause is that a characteristic of the output potential level of the potential comparing circuit against a fluctuation in the power source voltage, when both of the input potential levels are the same, differs from that of the next-stage logic circuit 10. That is, the output potential level of the potential comparing circuit is determined by an intersection of a characteristic curve of a MOS diode and the saturation current characteristic curve, while the determination potential level of the next-stage logic circuit 10 is determined by an intersection of saturation current characteristic curves of a p-type MOS transistor and an n-type MOS transistor, these transistors constituting the next-stage logic circuit 10.
FIGS. 2A and 2B are graphs showing drain voltage (V) - drain current (V.sub.I) characteristic curves Tr1, Tr2, Tr3, and Tr4 of the transistors 1, 2, 3 and 4, respectively. FIG. 2A shows curves obtained when the same potential V.sub.IN or V.sub.IN ' (V.sub.IN &gt;V.sub.IN ') is applied to each of the input terminals 7 and 8. In FIG. 2A, the graph on the left side shows characteristic curves of the input side of the current-mirror circuit 11, and the graph on the right side shows characteristic curves of the output side of the current-mirror circuit 11. FIG. 2B shows characteristic curves obtained when the same potential V.sub.IN is applied to each of the input terminals 7 and 8 and when the potential level of the power input terminal 5 of the current-mirror circuit side is varied from V.sub.CC to V.sub.CC '. In FIG. 2B, the graph on the left side shows characteristic curves of the input side of the current-mirror circuit 11, and the graph on the right side shows characteristic curves of the output side of the current-mirror circuit 11.
As shown in FIG. 2A, the output potential levels V.sub.T and V.sub.T ' are determined according to the potential levels at the input terminals 7 and 8, respectively. That is, as shown in the graph on the left side of FIG. 2, the output potential levels V.sub.T and V.sub.T ' are determined by an intersection of a MOS diode characteristic curve Tr1 of the transistor 1 and the saturation current characteristic curves Tr3 of the transistor 3. Since the MOS diode characteristic curve Tr1 of the transistor 1 inclines relative to a direction perpendicular to the V.sub.D axis, the drain voltage is shifted from V.sub.T to V.sub.T '. Accordingly, even if the characteristic of the transistors 1 and 2 are adjusted so that the output potential V.sub.T ', when the gate voltage V.sub.G of the transistor 3 is equal to V.sub.IN ', corresponds to the specific determination potential levels corresponding to "1" and "0" of the next-stage logic circuit 10, the output potential level is shifted to the higher potential level V.sub.T, and thus the determination error (offset) occurs.
Additionally, as shown in FIG. 2B, the characteristic curve Tr1 of the transistor 1 is shifted parallel by a difference between V.sub.CC and V.sub.CC ' in a direction along the V.sub.D axis. Accordingly, the output potential level of the potential comparing circuit is shifted from V.sub.T to V.sub.T ' in a direction along the V.sub.D axis.
On the other hand, the determination potential V.sub.LT of the next-stage logic circuit 10 is approximated as .alpha.V.sub.CC (V.sub.LT =.alpha.V.sub.CC), and V.sub.T ' is approximated as .alpha.V.sub.CC ' (V.sub.T '=.alpha.V.sub.CC '), where a is a constant less than 1 and V.sub.GND is equal to 0 volt. From the above, the following relationship is obtained. EQU V.sub.LT -V.sub.LT '=.alpha.(V.sub.CC -V.sub.CC ')
It is apparent from the above relationship, V.sub.LT -V.sub.LT ' is less than V.sub.T -V.sub.T ' because V.sub.T -V.sub.T ' is approximated as V.sub.CC -V.sub.CC '. Accordingly, even if V.sub.T is rendered to be equal to V.sub.LT by adjusting the characteristic of each of the transistors 1 and 2, the determination error may occur when the power source potential level changes to V.sub.CC '.